1.5v, .18u Area Efficient 32 Bit Adder using 4T XOR and Modified Manchester Carry Chain

The increasing demand for low power VLSI can be fulfilled to a great extent by making proper changes in the circuit level and architectural level design. Addition is a fundamental operation, as it is used to implement more complex functions such as subtraction, multiplication, division etc. The Manchester Carry Chain adder design is preferred to other adders, regardless the number of bits because of its high-speed and its wide applications. A new technique is presented in this paper for the implementation of a 32 bit Adder which operates at low power. Even though this implementation is structurally inherited from Manchester Carry Chain based Adder, it is highly area efficient without much increase in delay. The proposed adder is based on Multiple Output Domino logic, which helps to reduce the complexity of the adder implemented using Manchester Carry Chain adder implemented in CMOS logic. At the same time, the 4T implementations of XOR based circuits in the adder design results in lesser number of transistors for its implementation and thereby provide a low power/size solution for arithmetic functions. The simulation result shows a reduction of 23.4% in size, over CMOS adder implemented using the same Manchester Carry Chain topology at 1.5v Supply voltage with the help of TSMC .18u technology.